"Source Code Verification for Embedded Systems using Prolog."

Frank Flederer et al. (2017)

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DOI: 10.4204/EPTCS.234.7

access: open

type: Conference or Workshop Paper

metadata version: 2022-03-16

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  - journals/corr/FledererOSM17
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  - https://dblp.org/rec/journals/corr/FledererOSM17
Frank Flederer, Ludwig Ostermayer, Dietmar Seipel, Sergio Montenegro:
Source Code Verification for Embedded Systems using Prolog. WLP / WFLP 2017: 88-103

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