"An area-efficient low-power SCM topology for high performance network-on ..."

R. Poovendran, S. Sumathi (2019)

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DOI: 10.1002/CPE.4760

access: closed

type: Journal Article

metadata version: 2020-03-02

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R. Poovendran, S. Sumathi:
An area-efficient low-power SCM topology for high performance network-on Chip (NoC) architecture using an optimized routing design. Concurr. Comput. Pract. Exp. 31(14) (2019)

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