"FPGA friendly NoC simulation acceleration framework employing the hard blocks."

Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar (2021)

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DOI: 10.1007/S00607-020-00901-X

access: closed

type: Journal Article

metadata version: 2021-07-29

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Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
FPGA friendly NoC simulation acceleration framework employing the hard blocks. Computing 103(8): 1791-1813 (2021)

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