Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FPGA friendly NoC simulation acceleration framework employing the hard blocks."

Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar (2021)

> Home

Details and statistics

DOI: 10.1007/S00607-020-00901-X

access: closed

type: Journal Article

metadata version: 2021-07-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/computing/PrasadPT21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/computing/PrasadPT21
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
FPGA friendly NoC simulation acceleration framework employing the hard blocks. Computing 103(8): 1791-1813 (2021)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.