"Design of test pattern generator (TPG) by an optimized low power design ..."

G. Naveen Balaji, S. Chenthur Pandian (2019)

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DOI: 10.1007/S10586-018-2552-X

access: closed

type: Journal Article

metadata version: 2022-10-02

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G. Naveen Balaji, S. Chenthur Pandian:
Design of test pattern generator (TPG) by an optimized low power design for testability (DFT) for scan BIST circuits using transmission gates. Clust. Comput. 22(6): 15231-15244 (2019)

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