"PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA ..."

K. Rahimunnisa et al. (2013)

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DOI: 10.2478/S13537-013-0112-2

access: open

type: Journal Article

metadata version: 2023-09-30

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K. Rahimunnisa, P. Karthigaikumar, N. Anitha Christy, S. Suresh Kumar, J. Jayakumar:
PSP: Parallel sub-pipelined architecture for high throughput AES on FPGA and ASIC. Central Eur. J. Comput. Sci. 3(4): 173-186 (2013)

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