"A new floating-point adder FPGA-based implementation using RN-coding of ..."

Túlio Araujo et al. (2021)

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DOI: 10.1016/J.COMPELECENG.2020.106947

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type: Journal Article

metadata version: 2022-04-09

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Túlio Araujo, Matheus B. R. Cardoso, Erivelton G. Nepomuceno, Carlos H. Llanos, Janier Arias-Garcia:
A new floating-point adder FPGA-based implementation using RN-coding of numbers. Comput. Electr. Eng. 90: 106947 (2021)

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