"Design Method of Vertical Lattice Loop Structure for Parasitic Inductance ..."

Si-Seok Yang et al. (2022)

> Home

Details and statistics

DOI: 10.1109/ACCESS.2022.3220325

access: open

type: Journal Article

metadata version: 2022-12-05

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/access/YangMEKL22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/access/YangMEKL22
Si-Seok Yang, Sung-Soo Min, Chan-Hyeok Eom, Rae-Young Kim, Gi-Young Lee:
Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter. IEEE Access 10: 117215-117224 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.