"FPGA-Based Improved Background Subtraction for Ultra-Low Latency."

Yoshiyuki Oshima et al. (2024)

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DOI: 10.1109/ACCESS.2024.3483548

access: open

type: Journal Article

metadata version: 2024-11-30

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Yoshiyuki Oshima, Yoshiki Yamaguchi, Ryouhei Tsugami, Toshihito Fujiwara, Tatsuya Fukui, Satoshi Narikawa:
FPGA-Based Improved Background Subtraction for Ultra-Low Latency. IEEE Access 12: 164063-164080 (2024)

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