"A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration ..."

Leandro D. Medus et al. (2019)

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DOI: 10.1109/ACCESS.2019.2920885

access: open

type: Journal Article

metadata version: 2025-01-19

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Leandro D. Medus, Taras Iakymchuk, José Vicente Francés-Víllora, Manuel Bataller-Mompeán, Alfredo Rosado Muñoz:
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks. IEEE Access 7: 76084-76103 (2019)

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