"A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic ..."

Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat (2020)

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DOI: 10.1109/ACCESS.2019.2963727

access: open

type: Journal Article

metadata version: 2020-02-06

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Prashanth Barla, Vinod Kumar Joshi, Somashekara Bhat:
A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. IEEE Access 8: 6876-6889 (2020)

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