"SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using ..."

Arash Saifhashemi, Peter A. Beerel (2011)

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DOI: 10.3233/978-1-60750-774-1-287

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Arash Saifhashemi, Peter A. Beerel:
SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces. CPA 2011: 287-302

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