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"A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for ..."

Mohamed Badr Younis et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185437

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-12

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Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu:
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. VLSI Technology and Circuits 2023: 1-2

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