"A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving ..."

Zunsong Yang et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185259

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka:
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. VLSI Technology and Circuits 2023: 1-2

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