"An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and ..."

Angxiao Yan et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185335

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type: Conference or Workshop Paper

metadata version: 2024-10-06

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Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi:
An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits 2023: 1-2

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