"A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with ..."

Tomotaka Tanaka et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631525

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type: Conference or Workshop Paper

metadata version: 2024-10-17

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Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 3nm Fin-FET 19.87-Mbit/mm² 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. VLSI Technology and Circuits 2024: 1-2

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