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"Material, Process and System Level Analysis for Parasitic Reduction of ..."
Ashish Pal et al. (2024)
- Ashish Pal, Sefa Dag, Pratik B. Vyas, Gregory Costrini, Vinod Reddy, Veeraraghavan Basker, Allen Yeong, Benjamin Colombeau, Bala Haran, Subi Kengeri, El Mehdi Bazizi:
Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery. VLSI Technology and Circuits 2024: 1-2
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