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"Characterizing and Reducing the Layout Dependent Effect and Gate ..."
C. A. Lu et al. (2023)
- C. A. Lu, H. P. Lee, H. C. Chen, Y. C. Lin, Y. H. Chung, S. H. Wang, J. Y. Yeh, V. S. Chang, M. C. Chiang, W. Chang, H. C. Chung, C. F. Cheng, H. H. Hsu, H. H. Liu, William P. N. Chen, C. Y. Lin:
Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology. VLSI Technology and Circuits 2023: 1-2
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