"Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated ..."

Feng-Min Lee et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631386

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type: Conference or Workshop Paper

metadata version: 2024-10-17

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Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. VLSI Technology and Circuits 2024: 1-2

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