"5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O."

Kaveh Hosseini et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830221

access: closed

type: Conference or Workshop Paper

metadata version: 2024-06-06

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Kaveh Hosseini, Edwin Kok, Sergey Y. Shumarayev, Daniel Jeong, Allen Chan, Austin Katzin, Songtao Liu, Radek Roucka, Manan Raval, Minh Mac, Chia-Pin Chiu, Thungoc Tran, Kumar Abhishek Singh, Sangeeta Raman, Yanjing Ke, Chen Li, Li-Fan Yang, Paulo Chao, Haiwei Lu, Fernando Luna, Xiaoqian Li, Tim Tri Hoang, Arnab Sarkar, Asako Toda, Ravi Mahajan, Nitin Deshpande, Conor O'Keeffe, Uma Krishnamoorthy, Vladimir Stojanovic, Christopher Madden, Chong Zhang, Matt Sysak, Pavan Bhargava, Chen Sun, Mark Wade:
5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O. VLSI Technology and Circuits 2022: 260-261

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