"A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time ..."

J. Gu et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631527

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-17

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J. Gu, J. Ma, J. Guo, F. Guo, D. Liang, Y. Li, C. Shen, P. Gao, X. Zhang, J. Ding, M. Sorna, H. Wang, C. Cui, J. Troupe, P. Metty, Ken Chang:
A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring. VLSI Technology and Circuits 2024: 1-2

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