"Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back ..."

H. Fukutome et al. (2024)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46783.2024.10631539

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-17

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H. Fukutome, J. Kim, J. Shin, J. Kim, Y. Lee, Y. Park, D. Oh, S. Chae, B. Eom, YS Nam, M. Lee, S. Ha, EG Chung, J. Kim, M. Jo, SH Lee, S. Kim, KH Cho, KW Lee, DW Kim, HJ Cho, K. Rim, SD Kwon, J. Song:
Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node. VLSI Technology and Circuits 2024: 1-2

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