"A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - ..."

Yoonseo Cho et al. (2023)

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DOI: 10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185338

access: closed

type: Conference or Workshop Paper

metadata version: 2023-07-28

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Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi:
A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. VLSI Technology and Circuits 2023: 1-2

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