"Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit."

Pan Zhongliang (2004)

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DOI: 10.1109/ICVD.2004.1260970

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Pan Zhongliang:
Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit. VLSI Design 2004: 499-

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