"MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the ..."

Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy (1995)

> Home

Details and statistics

DOI: 10.1109/ICVD.1995.512087

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/YadavalliPR95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/YadavalliPR95
Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy:
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. VLSI Design 1995: 110-115

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.