"False Path and Clock Scheduling Based Yield-Aware Gate Sizing."

Jeng-Liang Tsai et al. (2005)

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DOI: 10.1109/ICVD.2005.99

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426

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