Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Surmounting Challenges in the Design of Low Power Real Time Clock IP for ..."

Krishnan Sukumar et al. (2023)

> Home

Details and statistics

DOI: 10.1109/VLSID57277.2023.00043

access: closed

type: Conference or Workshop Paper

metadata version: 2023-04-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsid/SukumarVAJGR23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/SukumarVAJGR23
Krishnan Sukumar, Santosh Vodnala, Ravindra Ayyagari, Animesh Jain, Thanapandi Ganesan, Rajesh R:
Surmounting Challenges in the Design of Low Power Real Time Clock IP for Advanced FinFET Technology Nodes. VLSID 2023: 157-162

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.