"Response Surface Modeling of 100nm CMOS Process Technology using Design of ..."

H. C. Srinivasaiah, Navakanta Bhat (2004)

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DOI: 10.1109/ICVD.2004.1260939

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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H. C. Srinivasaiah, Navakanta Bhat:
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. VLSI Design 2004: 285-290

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