"A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a ..."

Aatmesh Shrivastava et al. (2013)

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DOI: 10.1109/VLSID.2013.165

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Aatmesh Shrivastava, Jagdish Nayayan Pandey, Brian P. Otis, Benton H. Calhoun:
A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node. VLSI Design 2013: 72-75

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