"An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis."

Rupesh S. Shelar, Sachin S. Sapatnekar (2002)

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DOI: 10.1109/ASPDAC.2002.994890

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

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Rupesh S. Shelar, Sachin S. Sapatnekar:
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. ASP-DAC/VLSI Design 2002: 87-92

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