"An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled ..."

Ashesh Rastogi et al. (2007)

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DOI: 10.1109/VLSID.2007.32

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu:
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. VLSI Design 2007: 583-588

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