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"Modeling VHDL in Multiclock ESTEREL."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Basant Rajan, R. K. Shyamasundar (2000)

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DOI: 10.1109/ICVD.2000.812588

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Basant Rajan, R. K. Shyamasundar:
Modeling VHDL in Multiclock ESTEREL. VLSI Design 2000: 76-83

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last updated on 2023-03-24 00:04 CET by the dblp team

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