"A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay ..."

K. A. Rajagopal et al. (2006)

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DOI: 10.1109/VLSID.2006.8

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu:
A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. VLSI Design 2006: 277-282

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