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ORCID"Verification of Circuits Described in VHDL through Extraction of Design ..."
Yatin Vasant Hoskote et al. (1994)
- Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell:
Verification of Circuits Described in VHDL through Extraction of Design Intent. VLSI Design 1994: 417-420
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