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"Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells."

Avaneendra Gupta, John P. Hayes (1999)

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DOI: 10.1109/ICVD.1999.745197

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/vlsid/GuptaH99
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  persistent URL:
  - https://dblp.org/rec/conf/vlsid/GuptaH99
Avaneendra Gupta, John P. Hayes:
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. VLSI Design 1999: 453-459

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