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"A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS ..."

Avaneendra Gupta, John P. Hayes (1997)

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DOI: 10.1109/ICVD.1997.567954

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/vlsid/GuptaH97
Avaneendra Gupta, John P. Hayes:
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. VLSI Design 1997: 15-20

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