"Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and ..."

Ramen Dutta et al. (2010)

> Home

Details and statistics

DOI: 10.1109/VLSI.DESIGN.2010.78

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/DuttaBGK10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/DuttaBGK10
Ramen Dutta, Tarun Kanti Bhattacharyya, Xiang Gao, Eric A. M. Klumperink:
Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. VLSI Design 2010: 152-157

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.