"Design of an Optimal Test Pattern Generator for Built-in Self Testing of ..."

Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya (1998)

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DOI: 10.1109/ICVD.1998.646603

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya:
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. VLSI Design 1998: 205-

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