"Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random ..."

Arjun Singh Chauhan et al. (2020)

> Home

Details and statistics

DOI: 10.1109/VLSID49098.2020.00051

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsid/ChauhanSMD20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/ChauhanSMD20
Arjun Singh Chauhan, Vineet Sahula, A. S. Mandal, Abhigyan Dutta:
Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation. VLSID 2020: 195-200

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.