"80Kb 10ns read cycle logic Embedded High-K charge trap ..."

Janakiraman Viraraghavan et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573462

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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Janakiraman Viraraghavan, Derek Leu, Balaji Jayaraman, Alberto Cestero, Robert Kilker, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer:
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. VLSI Circuits 2016: 1-2

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