"A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS ..."

Tsung-Hsien Tsai et al. (2018)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2018.8502274

access: closed

type: Conference or Workshop Paper

metadata version: 2019-12-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/TsaiSCS18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/TsaiSCS18
Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski:
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. VLSI Circuits 2018: 183-184

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.