"A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS."

Saurabh Saxena et al. (2015)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2015.7231320

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/SaxenaSNTEAKCH15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/SaxenaSNTEAKCH15
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC 2015: 352-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.