"A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use ..."

Shinichi Moriwaki et al. (2012)

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DOI: 10.1109/VLSIC.2012.6243789

access: closed

type: Conference or Workshop Paper

metadata version: 2020-04-27

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Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara:
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC 2012: 60-61

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