"340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with ..."

Sanu Mathew et al. (2014)

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DOI: 10.1109/VLSIC.2014.6858420

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-25

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Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2⁴)² polynomials in 22nm tri-gate CMOS. VLSIC 2014: 1-2

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