"32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor ..."

Koki Ishida et al. (2020)

> Home

Details and statistics

DOI: 10.1109/VLSICIRCUITS18222.2020.9162826

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/IshidaTNOKTFI20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/IshidaTNOKTFI20
Koki Ishida, Masamitsu Tanaka, Ikki Nagaoka, Takatsugu Ono, Satoshi Kawakami, Teruo Tanimoto, Akira Fujimaki, Koji Inoue:
32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic. VLSI Circuits 2020: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.