"A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital ..."

Jay Im et al. (2018)

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DOI: 10.1109/VLSIC.2018.8502275

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

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Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. VLSI Circuits 2018: 145-146

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