"A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm2 ..."

Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das (2020)

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DOI: 10.1109/VLSICIRCUITS18222.2020.9162824

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-24

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Benjamin J. Fletcher, Terrence S. T. Mak, Shidhartha Das:
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm² 7.1mW/mm² Simultaneous Wireless Inter-Tier Data and Power Transfer. VLSI Circuits 2020: 1-2

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