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"An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL ..."
Mark A. Ferriss et al. (2012)
- Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu
, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman:
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177
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