"An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL ..."

Mark A. Ferriss et al. (2012)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2012.6243847

access: closed

type: Conference or Workshop Paper

metadata version: 2022-09-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/FerrissPNRPBYSV12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/FerrissPNRPBYSV12
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman:
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. VLSIC 2012: 176-177

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.