Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a ..."

Ming Ding et al. (2020)

> Home

Details and statistics

DOI: 10.1109/VLSICIRCUITS18222.2020.9162787

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/0003STTLB20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/0003STTLB20
Ming Ding, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Yao-Hong Liu, Christian Bachmann:
A 0.9pJ/Cycle 8ppm/°C DFLL-Based Wakeup Timer Enabled by a Time-Domain Trimming and An Embedded Temperature Sensing. VLSI Circuits 2020: 1-2

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.