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"A bit-sliced, scalable and unified montgomery multiplier architecture for ..."

M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas (2007)

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DOI: 10.1109/VLSISOC.2007.4402507

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas:
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC. VLSI-SoC 2007: 252-257

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