"Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs."

Sreenivaas S. Muthyala, Nur A. Touba (2014)

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DOI: 10.1007/978-3-319-25279-7_2

access: open

type: Conference or Workshop Paper

metadata version: 2018-06-26

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Sreenivaas S. Muthyala, Nur A. Touba:
Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs. VLSI-SoC (Selected Papers) 2014: 21-38

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